发明名称 |
Phase interpolator for a timing signal generating circuit |
摘要 |
A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period. |
申请公布号 |
US8065553(B2) |
申请公布日期 |
2011.11.22 |
申请号 |
US20090358861 |
申请日期 |
2009.01.23 |
申请人 |
TAMURA HIROTAKA;YAMAGUCHI HISAKATSU;WAKAYAMA SHIGETOSHI;GOTOH KOHTAROH;OGAWA JUNJI;FUJITSU LIMITED |
发明人 |
TAMURA HIROTAKA;YAMAGUCHI HISAKATSU;WAKAYAMA SHIGETOSHI;GOTOH KOHTAROH;OGAWA JUNJI |
分类号 |
G06F1/04;G11C11/407;G06F1/12;G06F1/24;G11C7/10;G11C7/22;G11C8/18;G11C11/4076;H03J7/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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