发明名称 MEMORY DEVICE ARCHITECTURES AND OPERATION
摘要 <p>Non-volatile memory devices logically organized to have erase blocks of at least two different sizes provide for concurrent erasure of multiple physical blocks of memory cells, while providing for individual selection of those physical blocks for read and program operations. In this manner, data expected to require frequent updating can be stored in locations corresponding to first erase blocks having a first size while data expected to require relatively infrequent updating can be stored in locations corresponding to second erase blocks larger than the first erase blocks. Storing data expected to require relatively more frequent updating in smaller logical memory blocks facilitates a reduction in unnecessary erasing of memory cells. In addition, by providing for larger logical memory blocks for storing data expected to require relatively less frequent updating, efficiencies can be obtained in erasing larger quantities of memory cells concurrently.</p>
申请公布号 KR101084820(B1) 申请公布日期 2011.11.21
申请号 KR20097018004 申请日期 2008.01.29
申请人 发明人
分类号 G11C16/16;G11C16/06;G11C16/14 主分类号 G11C16/16
代理机构 代理人
主权项
地址