发明名称 SEMICONDUCTOR PACKAGE CAPABLE OF COST REDUCTION AND MANUFACTURING METHOD THEREOF
摘要 <p>PURPOSE: A method for manufacturing a semiconductor package is provided to reduce manufacturing processes by omitting an additional plating process by forming a solder land on the first surface of a lead frame before the semiconductor chip is mounted. CONSTITUTION: A lead frame(100) for a semiconductor package includes a lead(106) and a chip mounting unit(104). A solder land(142,144) is smaller than the pattern width of the lead frame. A semiconductor chip(200) is mounted on the chip mount unit of the second surface(100b) of the lead frame. The semiconductor chip is connected to the lead of the lead frame by an Au wire(230). An encapsulant(240) encapsulates the second surface of the lead frame, the semiconductor chip, and the Au wire.</p>
申请公布号 KR20110125001(A) 申请公布日期 2011.11.18
申请号 KR20100044512 申请日期 2010.05.12
申请人 STS SEMICONDUCTOR & TELECOMMUNICATIONS CO., LTD. 发明人 JEONG, SANG JIN
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
主权项
地址
您可能感兴趣的专利