SAMPLE-AND-HOLD CIRCUIT AND A/D CONVERSION DEVICE

摘要

Disclosed is a sample-and-hold circuit and A/D conversion device such that occurrence of output saturation is avoided in relation to an input voltage of a power supply voltage range in a sample-and-hold circuit. The disclosed sample-and-hold circuit is provided with a first switch which is turned on at sampling time of an input voltage; a sampling capacitor for accumulating an input charge according to the input voltage in order to sample the input voltage which is input via the first switch when the first switch is on, and to accumulate a reference charge according to a predetermined reference voltage in order to sample the predetermined reference voltage when the first switch is off; an add-subtract means for adding or subtracting an input voltage sampled by the sampling capacitor and a predetermined reference voltage sampled by the sampling capacitor; and a hold means for holding and outputting the voltage that has been acquired by the addition or the subtraction by the add-subtract means.