| 摘要 |
An embodiment relates to a method (for example, a computer- implemented method) of designing an integrated circuit (IC). In this embodiment, layout data (400) describing conductive layers (404-1, 404-2, 404- 3, 404-4, 404-5) of the integrated circuit on a substrate (402) is generated according to design specification data for the integrated circuit. The conductive layers include a topmost layer of bond pads (406). Metal structures (408) in the layout data are modified to maximize metal density in a superimposed plane of the conductive layers (404-1, 404-2, 404-3, 404-4, 404-5) within a threshold volume under each of the bond pads (406). A description of the layout data (400) is generated on one or more masks for manufacturing the integrated circuit. By maximizing metal density in the superimposed plane, vertical channels through the dielectric material (412) in the interconnect are reduced or eliminated. Thus, alpha particles cannot readily penetrate the interconnect and reach the underlying substrate (402), reducing soft errors, such as single event upsets in memory cells. |
