发明名称 Method and apparatus for performing asynchronous and synchronous reset removal during synthesis
摘要 A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.
申请公布号 US2011283250(A1) 申请公布日期 2011.11.17
申请号 US20100800227 申请日期 2010.05.11
申请人 MANOHARARAJAH VALAVAN;ALTERA CORPORATION 发明人 MANOHARARAJAH VALAVAN
分类号 G06F17/50 主分类号 G06F17/50
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