| 摘要 |
<p>A processor has a data processing pipeline with several stages. The pipeline stages have error detectors. Each pipeline stage has two latches 26, 28 to hold the result of the stage. The result from a first instruction is placed in the first latch and the result from the next instruction in the pipeline is placed in the second latch. When an error is detected in the result in one latch, the value in that latch is corrected. The value in the other latch is unaffected. The output from the pipeline stage may be stored in a third shadow latch 36 after a time delay. The value in the shadow latch may be compared with the value in one of the main latches. If they are different, then an error is signaled. The value from the shadow latch may be copied to the main latch to correct the error.</p> |
