Hierarchical buffered segmented bit-lines based sram

摘要

A semiconductor memory device (1) comprising: a plurality of memory blocks (2) with memory cells (3) connected to a local bit-line (4a, 4b), each local bit-line being connectable to a global bit-line (5) for memory readout; pre-charging circuitry (24, 25, 26) for pre-charging the bit-lines; and a read buffer (17) for discharging the global bit-line during a read operation. The local bit-lines are pre-charged to a predetermined first voltage substantially lower than the supply voltage (VDD) of the memory device. A segment buffer (16) is provided between each local bit-line and an input node (18) of the respective read buffer. The segment buffer activates the read buffer (17) during the read operation upon occurrence of a discharge on the connected local bit-line.