发明名称 Methods of patterning insulating layers using etching techniques that compensate for etch rate variations
摘要 Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically insulating layer. First and second portions of the electrically insulating layer extending opposite the first and second openings, respectively, are simultaneously etched at first and second different etch rates. This etching yields a first trench extending adjacent the first opening that is deeper than a second trench extending adjacent the second opening. Then, the bottoms of the first and second trenches are simultaneously etched to substantially the same depths using an etching process that compensates for the first and second different etch rates.
申请公布号 US8058176(B2) 申请公布日期 2011.11.15
申请号 US20070861478 申请日期 2007.09.26
申请人 PARK WAN-JAE;KUMAR KAUSHIK ARUN;LINVILLE JOSEPH EDWARD;LISI ANTHONY DAVID;SRIVASTAVA RAVI PRAKASH;WENDT HERMANN WILLHELM;SAMSUNG ELECTRONICS CO., LTD.;INTERNATIONAL BUSINESS MACHINES CORPROATION;ADVANCED MICRO DEVICES CORPORATION;CHARTERED SEMICONDUCTOR MANUFACTURING LTD.;INFINEON TECHNOLOGIES AG 发明人 PARK WAN-JAE;KUMAR KAUSHIK ARUN;LINVILLE JOSEPH EDWARD;LISI ANTHONY DAVID;SRIVASTAVA RAVI PRAKASH;WENDT HERMANN WILLHELM
分类号 H01L21/311 主分类号 H01L21/311
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