Software based data flows addressing hardware block based processing requirements

摘要

In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.