发明名称 Generating multiple clock phases
摘要 In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.
申请公布号 US8058914(B2) 申请公布日期 2011.11.15
申请号 US20090511352 申请日期 2009.07.29
申请人 KRISTENSSON H. ANDERS;TZARTZANIS NESTOR;NEDOVIC NIKOLA;WALKER WILLIAM W.;FUJITSU LIMITED 发明人 KRISTENSSON H. ANDERS;TZARTZANIS NESTOR;NEDOVIC NIKOLA;WALKER WILLIAM W.
分类号 H03L7/06 主分类号 H03L7/06
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