发明名称 |
Semiconductor die structures for wafer-level chipscale packaging of power devices, packages and systems for using the same, and methods of making the same |
摘要 |
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention. |
申请公布号 |
US8058732(B2) |
申请公布日期 |
2011.11.15 |
申请号 |
US20080275086 |
申请日期 |
2008.11.20 |
申请人 |
GRUENHAGEN MICHAEL D.;KIM SUKU;MURPHY JAMES J.;HO IHSIU;TJHIA EDDY;WU CHUNG-LIN;LARSEN MARK;DIKSHIT ROHIT;FAIRCHILD SEMICONDUCTOR CORPORATION |
发明人 |
GRUENHAGEN MICHAEL D.;KIM SUKU;MURPHY JAMES J.;HO IHSIU;TJHIA EDDY;WU CHUNG-LIN;LARSEN MARK;DIKSHIT ROHIT |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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