发明名称 |
Vertical junction field effect transistors having sloped sidewalls and methods of making |
摘要 |
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation. |
申请公布号 |
US8058655(B2) |
申请公布日期 |
2011.11.15 |
申请号 |
US20090613065 |
申请日期 |
2009.11.05 |
申请人 |
SHERIDAN DAVID C.;RITENOUR ANDREW P.;SS SC IP, LLC |
发明人 |
SHERIDAN DAVID C.;RITENOUR ANDREW P. |
分类号 |
H01L29/24;H01L49/00 |
主分类号 |
H01L29/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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