发明名称 RECEIVING CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem that a conventional AD conversion circuit cannot properly control operation timing. <P>SOLUTION: A receiving circuit comprises: an AD conversion circuit having a differential amplifier for outputting a difference between an input analog signal and a reference voltage, an interpolation circuit in which the reference voltage interpolates an intermediate voltage of the sequential differential amplifier, a delay circuit for varying delay times of the output signals of the differential amplifier and the interpolation circuit, a determination circuit for converting the output signal of the delay circuit into a binary signal in response to a clock signal of a predetermined frequency, and an encoder for encoding the binary signal output from the determination circuit into digital data; an equalizing/decoding circuit for equalizing the digital signal output from the AD conversion circuit and decoding received data; and an adjustment circuit for changing the conversion timing of the AD conversion circuit and evaluating the output signal of the AD conversion circuit or the equalizing/decoding circuit and for selecting a conversion timing of the AD conversion circuit where the evaluation result falls within a predetermined range. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011228799(A) 申请公布日期 2011.11.10
申请号 JP20100094263 申请日期 2010.04.15
申请人 FUJITSU LTD 发明人 KIBUNE MASAYA
分类号 H03M1/36 主分类号 H03M1/36
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