发明名称 SYSTEM FOR CONCURRENT TEST OF SEMICONDUCTOR DEVICES
摘要 A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time.
申请公布号 US2011275170(A1) 申请公布日期 2011.11.10
申请号 US201113100889 申请日期 2011.05.04
申请人 TERADYNE, INC. 发明人 VAN WAGENEN BETHANY;EDWARD SENG J.
分类号 G06F19/00;H01L21/66 主分类号 G06F19/00
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