SMALL STANDBY TIME FIFO CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS SYSTEM

摘要

PROBLEM TO BE SOLVED: To provide an FIFO circuit having a small standby time and a high throughput.

SOLUTION: An FIFO circuit 100 includes a put interface 10 configured to operate according to a transmission side time area and a get interface 20 configured to operate according to a reception side time area. The FIFO circuit 100 includes the array of cells 170 each of which has a register and a state controller indicating the state of the cell. Each of the cells 170 also has a put configuring element section configured to operate according to the transmission side time area, including a put token passage circuit and a put controller circuit 176. Each of the cells 170 has a get configuring element section configured to operate according to the reception side time area including a get token passage circuit and a get controller circuit 178.

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