| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce capacitive coupling between active features. <P>SOLUTION: Selective placement of polishing dummy feature patterns is used, rather than indiscriminate placement of polishing dummy feature patterns, in the present invention. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns are specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for an active feature can be predicted. After polishing dummy feature patterns are arranged as seen in the exemplary figure, planarity can be examined on a local level (a portion but not all of the device) and a more wide-regional level (all of the device, devices corresponding to a reticle field, or even an entire wafer). <P>COPYRIGHT: (C)2012,JPO&INPIT |
