发明名称 VOLTAGE LEVEL SHIFTING WITH REDUCED POWER CONSUMPTION
摘要 In an embodiment, a voltage level shifter circuit includes a first terminal configured to be connected to a high voltage supply rail (Vs+), a second terminal configured to be connected to a low voltage supply rail (Vs−), and an output voltage (VOUT) terminal. The voltage level shifter can also include a compensation voltage (VCOMP) node. Additionally, the voltage level shifter includes a plurality of switches configurable in a plurality of configurations, and control circuitry configured to control the switches so that in at least one of the configurations a load connected to the output voltage (VOUT) terminal does not draw any power from the low voltage supply rail (Vs−) and the high voltage supply rail (Vs+). The load can be, e.g., a gate drive circuit of a display panel, such as a thin film transistor-liquid crystal display (TFT-LCD) panel, but is not limited thereto.
申请公布号 US2011273430(A1) 申请公布日期 2011.11.10
申请号 US201113021623 申请日期 2011.02.04
申请人 INTERSIL AMERICAS INC. 发明人 CHIA CHOR YIN;KIM HONG JOONG
分类号 G06F3/038;H03L5/00 主分类号 G06F3/038
代理机构 代理人
主权项
地址