| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital PLL whose power consumption is reduced as a digital PLL which outputs phase difference information in the form of a digital value. <P>SOLUTION: A digital PLL 100 comprises: an oscillator 10; an integral phase calculation unit 20; a decimal phase calculation unit 30; a phase difference calculation unit 40; a phase difference variation amount calculation monitor unit 50; and an oscillator control unit 60. The PLL decreases in variation amount of a phase difference as the output frequency of the oscillator approximates to a desired frequency set by a frequency division ratio, i.e. a lock state, so the phase difference variation amount calculation monitor unit 50 monitors a variation amount of the phase difference, thereby stopping the integral phase calculation unit 20 from performing counting operation once the variation amount becomes less than "1" which is less than 1 LSB of the integral phase calculation unit 20. <P>COPYRIGHT: (C)2012,JPO&INPIT |
