| 摘要 |
<p>A clock management circuit (205) has: an input unit (2051) for inputting a signal "CLK_i" serving as a reference signal; and a feedback signal line (2052) serving as a feedback path for feeding back, as a feedback signal "CLK_o", the signal "CLK_i" input from the input unit (2051). The clock management circuit (205) synchronizes the signal "CLK_i" input from the input unit (2051) with the feedback signal fed back from the feedback signal line (2052). A bit sequence output unit (210) outputs a predetermined bit sequence according to a synchronization time that was required for the clock management circuit (205) to synchronize the feedback clock signal "CLK_o" with the signal "CLK_i".</p> |
