发明名称 |
MEMORY-CONTROLLER-PARALLELISM-AWARE SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS |
摘要 |
Some embodiments of a processing system implement a memory-controller-parallelism-aware scheduling technique. In at least one embodiment of the invention, a method of operating a processing system includes scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor according to thread priority information associated with the plurality of threads. The thread priority information is based on a maximum of a plurality of local memory bandwidth usage indicators for each thread of the plurality of threads. Each of the plurality of local memory bandwidth usage indicators for each thread corresponds to a respective memory controller of a plurality of memory controllers.
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申请公布号 |
US2011276972(A1) |
申请公布日期 |
2011.11.10 |
申请号 |
US20100775643 |
申请日期 |
2010.05.07 |
申请人 |
CHUNG JAEWOONG;CHATTERJEE DEBARSHI |
发明人 |
CHUNG JAEWOONG;CHATTERJEE DEBARSHI |
分类号 |
G06F9/46 |
主分类号 |
G06F9/46 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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