| 摘要 |
<p>A memory cell array is constituted with a plurality of memory transistors (M11 to M22) having tunnel insulating films made relatively thick arranged in the form of a matrix, a non-selected column bias voltage of a value between a source voltage and a gate voltage when reading the selected transistor (M11) is supplied to the source and/or drain of a non-selected column memory transistor (M21) arranged in the column not containing the selected memory transistor (M11) in a reverse bias polarity to for example a channel forming region, and a voltage of a value between the voltage to be supplied to the gate of the related selected memory transistor (M11) when reading and a ground voltage supplied to the source of the selected memory transistor (M11). Further, a voltage equivalent to or lower than that for the source of the selected memory transistor (M11) is supplied to the gate of the non-selected row. <IMAGE></p> |
