发明名称 SYSTEM CAPABLE OF ADJUSTING CLOCK PHASE OF AD CONVERTER
摘要 <P>PROBLEM TO BE SOLVED: To provide an analog/digital converter with improved performance when clock noise interference is present. <P>SOLUTION: The system comprises a clock phase shifter 85 that is controlled so that a converter can operate at the optimum sampling time interval with respect to interference noise. The phase shifter comprises a device to generate multiple sampling clock phases and a multiplexer 82 that is connected to multiple phase inputs to select the optimum clock phase, and operates the analog/digital converter by selecting one of the optimum clock phase. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2011223589(A) 申请公布日期 2011.11.04
申请号 JP20110097513 申请日期 2011.04.25
申请人 THOMSON LICENSING 发明人 MARK FRANCIS RUMREICH;DAVID LAWRENCE ALBIN;JOHN WILLIAM GULEC
分类号 G06F1/06;H03M1/08;H03L7/00;H03M1/10;H03M1/12 主分类号 G06F1/06
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