| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data receiving circuit that can output data adaptable to both a fast data rate and a slow data rate on the basis of a single high-speed clock. <P>SOLUTION: In a receiver circuit 3, under a high-speed mode, a demultiplexer unit 33 generates parallel data of 33 bits and a clock #1 of 312.5 MHz in the high-speed mode from a data latch output of a data latch unit 31 on the basis of a clock of a clock signal generator 37. Under a low-speed mode, a boundary detection/low-speed data extracting unit 34 generates intermediate parallel data from the data latch output of the data latch unit 31, extracts bit data at a center portion, outputs parallel data of 4 bits in the low-speed mode, adjusts the clock on the basis of a data period ratio between the high-speed mode and the low-speed mode, and generates a clock #2 of 312.5 MHz. <P>COPYRIGHT: (C)2012,JPO&INPIT |
