| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an asynchronous pipeline type semiconductor memory. <P>SOLUTION: An SDRAM that is asynchronously pipelined includes separate pipeline stages which are controlled by asynchronous signals. Rather than using a clock signal to synchronize data in each stage, an asynchronous signal 28 is used to latch data in all stages. An asynchronous control signal is generated in a chip, and optimized to different waiting time stages 27. The data is synchronized to a clock at an end of a reading data path 24 before being read from the chip. Since the data is latched in each pipeline stage, a skew occurring in the data is smaller than ones found in a conventional wave pipeline architecture. In addition, since there is no relationship between the stages and a system clock CLK, the reading data path can be processed in any CAS waiting time only by forming a resynchronization output so as to support the reading data path. <P>COPYRIGHT: (C)2012,JPO&INPIT |
