| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that a circuit scale is increased. <P>SOLUTION: The clock signal adjustment circuit of a semiconductor integrated circuit comprises: a plurality of circuit blocks; a plurality of clock delay circuits for supplying clock signals obtained by delaying the input clock signals based on a delay control signal to the plurality of corresponding circuit blocks; a control circuit for executing the delay test of the plurality of circuit blocks; a relief group storage circuit for storing the information of the circuit block necessary for delay processing among the plurality of circuit blocks according to the result of the delay test; a prescribed number of delay setting circuit for storing delay value information of the circuit block whose delay processing is necessary among the plurality of circuit blocks according to the result of the delay test; and a delay setting assignment control circuit for assigning the delay control signal corresponding to the delay value information stored by the delay setting circuit to the clock delay circuit corresponding to the information of the circuit block stored by the relief group storage circuit. <P>COPYRIGHT: (C)2012,JPO&INPIT |
