| 摘要 |
An integrated circuit die includes a plurality of interconnects including a first test data input, a second test data input and a test dat a output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a further multiplexer coupled to the test data output, a multiplexer coupled to the first test data input and the second test data input, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer and a controller for controlling the multiplexer and the further multiplexer in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.
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