INVALID WRITE PREVENTION FOR STT-MRAM ARRAY

摘要

In a Spin Transfer Torque Magnetoresi stive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines. Write disturb is prevented by setting a voltage associated with unselected ones of the bit lines equal to a selected source line.