BLOCK AND STANDARD CELL PACKING METHOD FOR AUTOMATED DESIGN AREA OPTIMIZATION

摘要

The present invention relates to a hard block and to a standard cell packing method used for optimizing a design area during the designing of a semiconductor integrated circuit. A typical hard block packing method involves packing each block separately and has the limitation of being unable to completely ensure a success rate of interconnections between blocks or between a block and a standard cell. However, the present invention relates to: 1) a method for packing neighbor block groups by automatically recognizing a placement pattern of hard blocks; and 2) a method for obtaining an exclusive area with respect to standard cells by expanding the outline of each group, thereby improving the interconnection possibility between blocks or between a block and a standard cell of a reduced chip. Moreover, a typical standard cell packing method uses an incremental placement technique and has the limitation of maintaining the relative position of each standard cell in an original layout placement. According to the present invention, however, the incremental placement is optimized by using an alignment technique to maximally maintain an original relative position.