发明名称 |
PHASED NAND POWER-ON RESET |
摘要 |
A method and system for phasing power-intensive operations is disclosed. A non-volatile storage device controller detects a power reset. The controller is in communication with non-volatile memories in the non-volatile storage device. In response to detecting a power reset, the controller determines a current consumption necessary to reset the non-volatile memories in the non-volatile storage device. The controller simultaneously resets all of the non-volatile memories when the determined current consumption is less than a current consumption threshold. If the determined current consumption is greater than the current consumption threshold, the controller resets a first subset of the plurality of non-volatile memories, and after a predetermined delay, resets a second subset of the non-volatile memories. Therefore, a power-intensive operation may be performed without exceeding a current consumption threshold by dividing the operation into a sequence of steps that do not exceed the threshold.
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申请公布号 |
US2011271036(A1) |
申请公布日期 |
2011.11.03 |
申请号 |
US20100770358 |
申请日期 |
2010.04.29 |
申请人 |
CHENG STEVEN S;EA DENNIS;HUANG JIANMIN;MAK ALEXANDER KWOK-TUNG;MOOGAT FAROOKH |
发明人 |
CHENG STEVEN S.;EA DENNIS;HUANG JIANMIN;MAK ALEXANDER KWOK-TUNG;MOOGAT FAROOKH |
分类号 |
G06F12/00;G06F1/26;G06F12/02 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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地址 |
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