| 摘要 |
A mechanism is provided for increasing the scalability of formal verification solutions through enabling the use of input reparameterization on logic models that include memory arrays. A pre-processing mechanism enables the selection of a cut-based design partition which enables optimal reductions though input reparameterization given a netlist with constraints. A post-processing mechanism next prevents input reparameterization from creating topologically inconsistent models in the presence of arrays. Additionally, this technique may be used to rectify inconsistent topologies that may arise when reparameterizing even netlists without arrays, namely false sequential dependencies across initialization constructs. Furthermore, a mechanism is provided to undo the effects of memory array based input reparameterization on verification results.
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