发明名称 |
Invalid Write Prevention for STT-MRAM Array |
摘要 |
In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.
|
申请公布号 |
US2011267874(A1) |
申请公布日期 |
2011.11.03 |
申请号 |
US20100769995 |
申请日期 |
2010.04.29 |
申请人 |
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY;QUALCOMM INCORPORATED |
发明人 |
RYU KYUNGHO;KIM JISU;JUNG SEONG-OOK;KANG SEUNG H. |
分类号 |
G11C11/00;G11C7/22;G11C8/08;H01F7/06 |
主分类号 |
G11C11/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|