发明名称 |
SWITCHED CAPACITOR BASED NEGATIVE BITLINE VOLTAGE GENERATION SCHEME |
摘要 |
A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node. |
申请公布号 |
US2011267901(A1) |
申请公布日期 |
2011.11.03 |
申请号 |
US20100769694 |
申请日期 |
2010.04.29 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
YANG HSIU-HUI;LIU JACK;CHAN WEI MIN;CHOU SHAO-YU |
分类号 |
G11C5/14 |
主分类号 |
G11C5/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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