发明名称 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENTS
摘要 A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS1 and a MOS capacitor MOS2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP1 and a polysilicon capacitor PIP2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS1 constituting a lower electrode of the MOS capacitor MOS1 and a high-concentration semiconductor region HS2 constituting a lower electrode of the MOS capacitor MOS2 are coupled. Further, an electrode E1 constituting an upper electrode of the MOS capacitor MOS1 is coupled to the low potential (for example, GND) and an electrode E3 constituting an upper electrode of the MOS capacitor MOS2 is coupled to the high potential (for example, power source potential).
申请公布号 US2011269291(A1) 申请公布日期 2011.11.03
申请号 US201113179474 申请日期 2011.07.08
申请人 RENESAS ELECTRONICS CORPORATION 发明人 UENO MAYA
分类号 H01L21/02 主分类号 H01L21/02
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