| 摘要 |
An all-digital phase-locked loop (ADPLL) composed of digital circuits is provided. The ADPLL includes a phase-frequency detector (PFD), a control unit, a digital controlled oscillator (DCO), and a plurality of frequency dividers. A first frequency divider divides a frequency of a feedback signal CKOUT by a natural number M to generate a first output signal CKOUT/M. The PFD generates a decrement signal dn and an increment signal up, based on a phase difference and a frequency between a first reference clock signal CKIN and the first output signal CKOUT/M. The DCO generates a clock signal CKDCO based on the digital control signals. A second frequency divider receives the digital control signals from the control unit and the CKDCO from the DCO and divides the frequency of the CKDCO by a bit number of the digital control signals to generate a feedback signal CKOUT to the first frequency divider.
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