| 摘要 |
The dynamic read/write memory device includes a memory scheme including a set of DRAM memory cells including a plurality of memory cell lines, and line selection means associated with each line; the line selection means including a first voltage-raising stage (ET1A, ET1B) configured to receive two initial logic signals (DEC0, PHI1) each having an initial voltage level corresponding to a first logic state and to deliver two intermediate control logic signals (DEC1, PHI1) each having an intermediate voltage greater than said initial level and corresponding to said initial logic state, and a control circuit (CCM) with voltage-raising intended to be supplied by means of PMOS transistors with a supply voltage having a second voltage level greater than the intermediate level, and configured to, in the presence of the two intermediate control logic signals (DEC1, PHI1) in the first logic state thereof, deliver to the transistor gates of the memory cells of said line (WL), a selection logic signal (SWL) having the second voltage level. |
