发明名称 |
MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE |
摘要 |
The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks. |
申请公布号 |
US2011260751(A1) |
申请公布日期 |
2011.10.27 |
申请号 |
US201113176284 |
申请日期 |
2011.07.05 |
申请人 |
ALTERA CORPORATION |
发明人 |
LEE ANDY L.;JOHNSON BRIAN D. |
分类号 |
H03K19/173 |
主分类号 |
H03K19/173 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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