发明名称 METHOD FOR EVALUATING PATTERN LAYOUT AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method for evaluating a pattern layout for accurately calculating a pattern formation defect region caused by a step pattern, in a short time.SOLUTION: The method for evaluating a pattern layout comprises: calculating a pattern formation defect region by using a correspondence relation between a distance from a pattern formed through a lithographic process in a formed film covering a step portion to the step portion, and the possibility that the formed pattern becomes a pattern formation defect region, and by using the layout of the step portion; and extracting a pattern formation defect region by comparing the calculated pattern formation defect region and the layout of the formed pattern. The correspondence relation is a function representing the correspondence relation, and is prepared based on the exposure conditions or process conditions for forming the step portion. The pattern formation defect region is calculated by performing convolution operation of the correspondence relation on the layout used for forming the step portion.
申请公布号 JP2011215627(A) 申请公布日期 2011.10.27
申请号 JP20110127221 申请日期 2011.06.07
申请人 TOSHIBA CORP 发明人 TAKAHASHI MASANORI;KOTANI TOSHIYA;TANAKA SATOSHI
分类号 G03F1/36;G03F1/68;G03F1/70;H01L21/027 主分类号 G03F1/36
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