发明名称 |
SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES |
摘要 |
Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor. |
申请公布号 |
WO2011087589(A3) |
申请公布日期 |
2011.10.27 |
申请号 |
WO2010US58236 |
申请日期 |
2010.11.29 |
申请人 |
INTEL CORPORATION;DIXON, MARTIN G.;RODGERS, SCOTT D. |
发明人 |
DIXON, MARTIN G.;RODGERS, SCOTT D. |
分类号 |
G06F12/08;G06F9/312 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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