发明名称 |
BALANCING A SIGNAL MARGIN OF A RESISTANCE BASED MEMORY CIRCUIT |
摘要 |
<p>A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.</p> |
申请公布号 |
EP2380175(A1) |
申请公布日期 |
2011.10.26 |
申请号 |
EP20090802075 |
申请日期 |
2009.12.18 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
JUNG, SEONG-OOK;KIM, JISU;SONG, JEE-HWAN;KANG, SEUNG H.;YOON, SEI SEUNG;SANI, MEHDI HAMIDI |
分类号 |
G11C11/16 |
主分类号 |
G11C11/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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