| 摘要 |
A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between −100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.
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