| 摘要 |
A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.
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