发明名称 |
Memory cell array |
摘要 |
A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level. |
申请公布号 |
US8045410(B2) |
申请公布日期 |
2011.10.25 |
申请号 |
US20090434084 |
申请日期 |
2009.05.01 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
KAPRE RAVINDRA M.;SHARIFZADEH SHAHIN |
分类号 |
G11C7/02;G11C5/14;G11C11/34;H01L27/092;H02H9/02 |
主分类号 |
G11C7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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