发明名称 |
METHOD AND APPARATUS FOR AC SCAN TESTING WITH DISTRIBUTED CAPTURE AND SHIFT LOGIC |
摘要 |
An integrated circuit device includes a plurality of functional tiles. Each functional tile may be configured into a scan chain. A clock generator is operable to generate an internal clock signal that is distributed to each of the functional tiles. A clock gater is associated with each of the functional tiles. Each clock gater is operable to receive an external enable signal and the internal clock signal, generate a scan clock signal for loading a test pattern into the scan chain based on the external enable signal and the internal clock signal, and generate at least one capture clock signal for capturing a response of the tile to the test pattern responsive to identifying the loading of the test pattern.
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申请公布号 |
US2011258505(A1) |
申请公布日期 |
2011.10.20 |
申请号 |
US20100761573 |
申请日期 |
2010.04.16 |
申请人 |
MAJUMDAR AMITAVA;GANTI VASU |
发明人 |
MAJUMDAR AMITAVA;GANTI VASU |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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