发明名称 |
Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry |
摘要 |
A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values.
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申请公布号 |
US2011258498(A1) |
申请公布日期 |
2011.10.20 |
申请号 |
US20100762048 |
申请日期 |
2010.04.16 |
申请人 |
SYNOPSYS, INC. |
发明人 |
CHANDRA ANSHUMAN;SAIKIA JYOTIRMOY;KAPUR ROHIT |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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