发明名称 |
Flip-Flop and Frequency Dividing Circuit with Flip-Flop |
摘要 |
Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.
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申请公布号 |
US2011254595(A1) |
申请公布日期 |
2011.10.20 |
申请号 |
US201113087021 |
申请日期 |
2011.04.14 |
申请人 |
MSTAR SEMICONDUCTOR, INC. |
发明人 |
SUN WEIGANG |
分类号 |
H03B19/06;H03K3/00;H03K3/356 |
主分类号 |
H03B19/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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