| 摘要 |
In a video signal processing device, a host CPU sets a number of parameters for a memory table at its low-load timing such as during power-up. The host CPU then enables the function of an automatic setting controller. Being notified of start of automatic setting, the automatic setting controller reads plural clock setting parameters from the memory table, and performs clock setting in a clock generation section while waiting for stabilization of PLL oscillation. The automatic setting control section then reads plural signal processing parameters from the memory table and sets the parameters in a video signal processing section. Thus, in operation of the video signal processing section and the clock generation section according to the format of the input video signal, it is possible to set a number of setting parameters in these sections while reducing the load of the host CPU, shortening the image output time.
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