| 摘要 |
A computer processor 100 is provided which hides jump instructions, in particular condition jump instructions, from side-channels. The processor comprises a forward jump detector 254 for detecting a forward jump instruction having a jump target location which lies ahead and a jump inhibitor 262 for inhibiting an execution of the forward jump instruction. The computer processor is configured for executing at least one intermediate computer instruction located between the inhibited forward jump instruction and the jump target location. The processor further comprises a storage destination modifier 260, 262 for modifying the storage destination determined by the at least one intermediate computer instruction to suppress the effects of execution of intermediate instructions. Since the intermediate instruction is executed regardless of the forward jump instruction, the jump is hidden in a side-channel. Secret information, such as cryptographic keys, on which the forward jump may depend, is also hidden. |
