| 摘要 |
A shift register includes a plurality of first to n-numbered stages, where n is a positive integer. Each stage includes a node controller controlling respective voltages of a first node and a second node in accordance with an output signal from the (i−j1)-numbered stage and an output signal from the (i+j2)-numbered stage, wherein i is a positive integer from 1 to n, j1 is a positive integer greater than or equal to 2, and j2 is a positive integer equal to or different from j1; and an output unit outputting one of a plurality of clock signals in accordance with the respective voltages of the first and second nodes.
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