| 摘要 |
Aspects of a method and system for RF signal generation utilizing a synchronous multi-modulus divider are provided. In this regard, a feedback signal of a PLL may be generated by clocking a counter with an RF signal output by the PLL and toggling the feedback signal each time a determined value of the counter is reached. Moreover, updates of each register in the counter and transitions of the feedback signal may be synchronous with the RF signal output by the PLL. The PLL may be part of a cellular transmitter and/or receiver which may communicate over an EDGE network. A counting sequence of the counter may be determined, at least in part, by an output of a &Dgr;&Sgr; modulator. In this regard, a first counting sequence may be utilized when an output of the &Dgr;&Sgr; modulator may be asserted and a second counting sequence may be utilized when the output of &Dgr;&Sgr; modulator may be de-asserted.
|
